ISO 9001

EXTERNAL REFERENCE PLDRO

This page provides information on our Phase Locked Dielectric Resonator Oscillator (PLDRO) series PLO-2000 EXTERNAL REFERENCE PLDRO.

PLO-2000 Photo Features
Application
Description
Specification
Phase Noise Envelope
Block Diagram
Outline Drawing










 

FEATURES
DIELECTRIC RESONATOR
INTERNAL VOLTAGE REGULATOR
PHASE LOCK INDICATOR ALARM
LOW PHASE NOISE
MIC AND SMT FABRICATION ON ALUMINA CIRCUIT BOARD
LOW MICROPHONICS
LOW POWER CONSUMPTION
UP TO +22 dBm OUTPUT POWER
AVAILABLE FROM 2.8 - 40 GHz
OPERATING RANGE -55o TO +105oC

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APPLICATION
SATELLITE COMMUNICATIONS
CABLE TV LINKS (CATV)
LOCAL AREA NETWORKS (LAN)
GLOBAL POSITIONING SYSTEMS (GPS)
TEST EQUIPMENT
TRAFFIC SIGN POSTS
POLICE RADARS
TRANSMITTER & RECEIVERS
DIGITAL RADIOS
MISSILE GUIDANCE
POINT TO POINT
MILITARY, SPACE, COMMERCIAL

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DESCRIPTION



PLO-2000 series Phase Locked Dielectric Resonator Oscillator (PLDRO) utilizes state of the art MIC and SMT to provide crystal stability at microwave frequencies up to 40 GHz. The low profile and rugged construction provide excellent durability against harsh environmental conditions.


PLO-2000 series oscillator is designed using GaAs FET or BJT amplifier with series feedback at source and Dielectric Resonator at the gate. High gain, low-noise GaAs FETs/BJTs are biased positively or negatively at the gate to ensure minimum phase-noise. The device is carefully matched for maximum power, minimum phase-noise and Voltage standing-Ratio (VSWR). The oscillator is matched for maximum temperature stability and optimum negative resistance.


PLO-2000 series oscillator is buffered by cascaded low-noise driver and power amplifiers for minimum load pulling, maximum isolation and power. GaAs FET/BJT devices are directly attached to gold plated Kovar carriers to minimize shear effect and maximize heat sinking. Kovar carriers are soldered to the chassis to provide an efficient thermal junction and a stable structure for reduction of microphonics. To ensure oscillator stability over the full temperature range, the tuning elements are precisely designed and positioned to compensate for temperature drift by a factor of three.


PLO-2000 series proprietary Phase lock loop circuitry is a surface mountprinted circuit board. The reference frequency is multiplied and sampled to output frequency. Produced error voltage due to frequency drift is sensed by a Wein-Bridge Oscillator to provide the necessary sweep voltage to an ultra Hi-Q tuning varactor diode for the purpose of compensation and phase locking. The unique construction of phase lock loop sub-assembly provides excellent temperature stability and minimum solder joints for maximum reliability.


PLO-2000 series is internally voltage regulated to avoid reverse bias, frequency pushing, bias modulation and voltage transients. A phase lock indicator alarm of open collector type is provided as a feature. The PLO-2000 series are externally reference locked and factory tuned to specified frequency. Mechanical frequency adjustment is provided for optimum phase voltage setting.

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SPECIFICATIONS
Model Number PLO-2000-XX.XX
Single Frequency 3.00 to 50.00 GHz
Mechanical Tuning Range 100 MHz
Power Output +13 dBm, up to +25 dBm Optional
Load VSWR, Maximum 2.0 : 1.0
Power Requirements 12, +15 VDC, 220 mA
Reference Input Frequency 50 To 200 MHz
Reference Power Input Nominal +/- 6 dBm
Reference Power Input Range -6 To +10 dBm
Frequency Stability Same as reference
Phase Noise Ref Noise + 20 log(N) + 3dB
Spurious -80 dBc
Harmonics -25 dBc
Alarm TTL
Operating Temperature -50o to +105oC Optional; 0o to 50o Standard
Storage Temperature -55o to +125oC
Connectors SMA Female or 2.9 mm
Size 2.25" x 2.25" x .67"
Finish Nickel

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PHASE NOISE ENVELOPE




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BLOCK DIAGRAM


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OUTLINE DRAWING


For updated outline drawings, please check with the factory.







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14321 Chambers Road
Tustin, California 92780 USA
Phone: 714-505-0998 Fax: 714-505-0994
Email: info@microwave-dynamics.com